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19-5036; rev 5; 1/11 max11044/MAX11045/max11046/ max11054/max11055/max11056 4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. general description the max11044/MAX11045/max11046 16-bit and max11054/max11055/max11056 14-bit adcs offer 4, 6, or 8 independent input channels. featuring independent track and hold (t/h) and sar circuitry, these parts pro- vide simultaneous sampling at 250ksps for each channel. the max11044/MAX11045/max11046 and max11054/ max11055/max11056 accept a 5v input. all inputs are overrange protected with internal 20ma input clamps providing overrange protection with a simple external resistor. other features include a 4mhz t/h input bandwidth, internal clock, and internal or external reference. a 20mhz, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs. the max11044/MAX11045/max11046 and max11054/ max11055/max11056 operate with a 4.75v to 5.25v analog supply and a separate flexible 2.7v to 5.25v digital supply for interfacing with the host without a level shifter. the max11044/MAX11045/max11046 are available in a 56-pin tqfn and 64-pin tqfp pack- ages while the max11054/max11055/max11056 are available in tqfp only and operate over the extended -40c to +85c temperature range. applications automatic test equipment power-factor monitoring and correction power-grid protection multiphase motor control vibration and waveform analysis features 16-bit adc (max11044/MAX11045/max11046) and 14-bit adc (max11054/max11055/max11056) 8-channel adc (max11046/max11056) 6-channel adc (MAX11045/max11055) 4-channel adc (max11044/max11054) single analog and digital supply high-impedance inputs up to 1g ? on-chip t/h circuit for each channel fast 3 s conversion time high throughput: 250ksps for each channel 16-bit/14-bit, high-speed, parallel interface internal clocked conversions 10ns aperture delay 100ps channel-to-channel t/h matching low drift, accurate 4.096v internal reference providing an input range of ?v external reference range of 3.0v to 4.25v, allowing full-scale input ranges of ?.0v to ?.2v 56-pin (8mm x 8mm) tqfn and 64-pin (10mm x 10mm) tqfp packages evaluation kit available ordering information part pin-package channels max11044 etn+ 56 tqfn-ep* 4 max11044ecb+ 64 tqfp-ep* 4 MAX11045 etn+ 56 tqfn-ep* 6 MAX11045ecb+ 64 tqfp-ep* 6 max11046 etn+ 56 tqfn-ep* 8 max11046ecb+ 64 tqfp-ep* 8 max11054 ecb+ 64 tqfp-ep* 4 max11055 ecb+ 64 tqfp-ep* 6 max11056 ecb+ 64 tqfp-ep* 8 note: all devices are specified over the -40c to +85c operating temperature range. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. functional diagram clamp s/h 16-/14-bit adc clamp s/h 16-/14-bit adc ref buf configuration registers interface and control bandgap reference 8 x 16-/1 4-bit registers bidirectional dr ivers ch0 avdd agnds agnd ch7 ? db15** db0/cr0 db3/cr3 db4 eoc shdn convst cs rd wr dgnd dvdd rdc rdc_sense* **max11044/MAX11045/max11046 ? max11046/max11056 refio int ref 10k ? ext ref *connected internally to rdc on the tqfn parts max11044/MAX11045/max11046/ max11054/max11055/max11056 pin configurations appear at end of data sheet.
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 2 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 absolute maximum ratings electrical characteristics (v avdd = +4.75v to +5.25v, v dvdd = +2.70v to +5.25v, v agnds = v agnd = v dgnd = 0v, v refio = internal reference, c rdc = 4 x 33f, c refio = 0.1f, c avdd = 4 x 0.1f || 10f, c dvdd = 3 x 0.1f || 10f; all digital inputs at dvdd or dgnd, unless otherwise noted, f sample = 250ksps. t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd to agnd ........................................................-0.3v to +6v dvdd to agnd and dgnd .....................................-0.3v to +6v dgnd to agnd.....................................................-0.3v to +0.3v agnds to agnd...................................................-0.3v to +0.3v ch0Cch7 to agnd ...............................................-7.5v to +7.5v refio, rdc to agnd ..................................-0.3v to the lower of (v avdd + 0.3v) and +6v eoc , wr , rd , cs , convst to agnd.........-0.3v to the lower of (v dvdd + 0.3v) and +6v db0Cdb15 to agnd ....................................-0.3v to the lower of (v dvdd + 0.3v) and +6v maximum current into any pin except avdd, dvdd, agnd, dgnd ...........................................................................50ma continuous power dissipation 56-pin tqfn (derate 47.6mw/c above +70c) ....3809.5mw 64-pin tqfp (derate 43.5mw/c above +70c)........3478mw operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units static performance (note 1) max11044/MAX11045/max11046 16 resolution n max11054/max11055/max11056 14 bits max11044/MAX11045/max11046 > -2 0.4 < +2 integral nonlinearity inl max11054/max11055/max11056 -0.8 0.13 +0.8 lsb max11044/MAX11045/max11046 > -1 0.4 < +1.2 differential nonlinearity dnl max11054/max11055/max11056 -0.6 0.15 +0.6 lsb max11044/MAX11045/max11046 16 no missing codes max11054/max11055/max11056 14 bits offset error 0.001 0.015 %fsr channel offset matching 0.001 0.015 %fsr offset temperature coefficient 0.8 v/c gain error 0.015 %fsr positive full-scale error 0.015 %fsr negative full-scale error 0.015 %fsr positive full-scale error matching 0.01 %fsr negative full-scale error matching 0.01 %fsr channel gain-error matching between all channels 0.01 %fsr gain temperature coefficient 0.5 ppm/c dynamic performance m ax 11044/m ax 11045/ max11046 91 92.3 signal-to-noise ratio snr f in = 10khz, full-scale input m ax 11054/m ax 11055/ max11056 84.5 85.2 db m ax 11044/m ax 11045/ max11046 90.5 92 signal-to-noise and distortion ratio sinad f in = 10khz, full-scale input m ax 11054/m ax 11055/ max11056 84.5 85.2 db
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 3 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 electrical characteristics (continued) (v avdd = +4.75v to +5.25v, v dvdd = +2.70v to +5.25v, v agnds = v agnd = v dgnd = 0v, v refio = internal reference, c rdc = 4 x 33f, c refio = 0.1f, c avdd = 4 x 0.1f || 10f, c dvdd = 3 x 0.1f || 10f; all digital inputs at dvdd or dgnd, unless otherwise noted, f sample = 250ksps. t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units m ax 11044/m ax 11045/ max11046 98 104 spurious-free dynamic range sfdr f in = 10khz, full-scale input m ax 11054/m ax 11055/ max11056 95 104 db m ax 11044/m ax 11045/ max11046 -105 -98 total harmonic distortion thd f in = 10khz, full-scale input m ax 11054/m ax 11055/ max11056 -104 -95 db channel-to-channel crosstalk f in = 60hz, full scale and ground on adjacent channel (note 2) -126 -100 db analog inputs (ch0?h7) input voltage range (note 3) 1.22 x v refio v input leakage current -1 +1 a input capacitance 15 pf input-clamp protection current each input simultaneously -20 +20 ma track and hold throughput rate per channel 1 250 ksps acquisition time t acq 1 1000 s -3db point 4 full-power bandwidth -0.1db point > 0.2 mhz aperture delay 10 ns aperture-delay matching 100 ps aperture jitter 50 ps rms internal reference refio voltage v ref 4.08 4.096 4.112 v refio temperature coefficient 5 ppm/c external reference input current -10 +10 a ref voltage-input range v ref 3.00 4.25 v ref input capacitance 15 pf digital inputs (cr0?r3, rd , wr , cs , convst) input voltage high v ih v dvdd = 2.7v to 5.25v 2 v input voltage low v il v dvdd = 2.7v to 5.25v 0.8 v input capacitance c in 10 pf input current i in v in = 0v or v dvdd 10 a
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 4 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 electrical characteristics (continued) (v avdd = +4.75v to +5.25v, v dvdd = +2.70v to +5.25v, v agnds = v agnd = v dgnd = 0v, v refio = internal reference, c rdc = 4 x 33f, c refio = 0.1f, c avdd = 4 x 0.1f || 10f, c dvdd = 3 x 0.1f || 10f; all digital inputs at dvdd or dgnd, unless otherwise noted, f sample = 250ksps. t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units digital outputs (db0?b15, eoc ) output voltage high v oh i source = 1.2ma v dvdd - 0.4 v output voltage low v ol i sink = 1ma 0.25 0.4 v three-state leakage current db0Cdb15, v rd v ih or v cs v ih 10 a three-state output capacitance db0Cdb15, v rd v ih or v cs v ih 15 pf analog supply voltage avdd 4.75 5.25 v digital supply voltage dvdd 2.70 5.25 v max11046/max11056, v avdd = 5v 48 MAX11045/max11055, v avdd = 5v 39 analog supply current i avdd max11044/max11054, v avdd = 5v 30 ma max11046/max11056, v dvdd = 3.3v 7.0 MAX11045/max11055, v dvdd = 3.3v 6.5 digital supply current (note 9) i dvdd max11044/max11054, v dvdd = 3.3v 5.5 ma i dvdd 10 shutdown current i avdd 10 a max11044/MAX11045/ max11046 1 power-supply rejection psr v avdd = 4.9v to 5.1v (note 5) max11054/max11055/ max11056 0.25 lsb timing characteristics (note 4) convst rise to eoc t con conversion time (note 6) 3 s acquisition time t acq 1 1000 s cs rise to convst rise t q sample quiet time (note 6) 500 ns convst rise to eoc rise t 0 47 140 ns eoc fall to convst fall t 1 convst mode b0 = 0 only (note 7) 0 ns convst low time t 2 convst mode b0 = 1 only 20 ns cs fall to wr fall t 3 0ns wr low time t 4 20 ns cs rise to wr rise t 5 0ns input data setup time t 6 10 ns input data hold time t 7 1ns cs fall to rd fall t 8 0ns rd low time t 9 30 ns
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 5 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 electrical characteristics (continued) (v avdd = +4.75v to +5.25v, v dvdd = +2.70v to +5.25v, v agnds = v agnd = v dgnd = 0v, v refio = internal reference, c rdc = 4 x 33f, c refio = 0.1f, c avdd = 4 x 0.1f || 10f, c dvdd = 3 x 0.1f || 10f; all digital inputs at dvdd or dgnd, unless otherwise noted, f sample = 250ksps. t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units rd rise to cs rise t 10 0ns rd high time t 11 10 ns rd fall to data valid t 12 35 ns rd rise to data hold time t 13 (note 7) 5 ns note 1: see the definitions section at the end of the data sheet. note 2: tested with alternating channels modulated at full scale and ground. note 3: see the input range and protection section for more details. note 4: c load = 30pf on db0Cdb15 and eoc. inputs (ch0Cch7) alternate between full scale and zero scale. f conv = 250ksps. all data is read out. note 5: defined as the change in positive full scale caused by a 2% variation in the nominal supply voltage. note 6: it is recommended that rd , wr , and cs are kept high for the quiet time (t q ) and conversion time (t con ). note 7: guaranteed by design. integral nonlinearity vs. code (max1104_) max11044 toc01 output code (decimal) inl (lsb) 57344 49152 32768 40960 16384 24576 8192 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 65536 v avdd = 5.0v v dvdd = 3.3v f sample = 250ksps t a = +25c v rdc = 4.096v differential nonlinearity vs. code (max1104_) max11044 toc02 output code (decimal) dnl (lsb) 57344 49152 32768 40960 16384 24576 8192 -0.800 -0.600 -0.400 -0.200 0 0.200 0.400 0.600 0.800 1.000 -1.000 0 65536 v avdd = 5.0v v dvdd = 3.3v f sample = 250ksps t a = +25c v rdc = 4.096v inl and dnl vs. analog supply voltage (max1104_) max11044 toc03 v avdd (v) inl and dnl (lsb) 5.15 5.05 4.95 4.85 -0.6 -0.2 0.2 0.6 1.0 -1.0 4.75 5.25 v dvdd = 3.3v f sample = 250ksps t a = +25c v rdc = 4.096v max inl max dnl min dnl min inl typical operating characteristics (v avdd = 5v, v dvdd = 3.3v, t a = +25c, f sample = 250ksps, internal reference, unless otherwise noted.)
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 6 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 typical operating characteristics (continued) (v avdd = 5v, v dvdd = 3.3v, t a = +25c, f sample = 250ksps, internal reference, unless otherwise noted.) analog supply current vs. supply voltage max11044 toc05 v avdd (v) i avdd (ma) 5.15 5.05 4.95 4.85 25 30 35 40 45 20 4.75 5.25 t a = +25c f sample = 250ksps max11046 converting MAX11045 converting max11044 converting max11046 static MAX11045 static max11044 static digital supply current vs. supply voltage max11044 toc07 v dvdd (v) i dvdd (ma) 4.75 4.25 3.75 3.25 2 4 6 8 10 12 0 2.75 5.25 t a = +25c f sample = 250ksps max11046 converting max11044/MAX11045/max11046 static MAX11045 converting max11044 converting inl and dnl vs. temperature (max1104_) max11044 toc04 temperature (c) inl and dnl (lsb) 60 35 10 -15 -1.0 -0.5 0 0.5 1.0 1.5 -1.5 -40 85 v avdd = 5.0v v dvdd = 3.3v f sample = 250ksps v rdc = 4.096v max dnl min dnl max inl min inl analog supply current vs. temperature max11044 toc06 temperature (c) i avdd (ma) 60 35 10 -15 25 30 35 40 45 20 -40 85 v avdd = 5.0v f sample = 250ksps max11046 converting MAX11045 converting max11044 converting max11046 static MAX11045 static max11044 static
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 7 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 digital supply current vs. temperature max11044 toc08 temperature (c) i dvdd (ma) 60 35 10 -15 1.2 2.4 3.6 4.8 6.0 7.2 0 -40 85 v dvdd = 3.3v f sample = 250ksps c dbxx = 15pf max11046 converting max11044/MAX11045/max11046 static MAX11045 converting max11044 converting analog and digital shutdown current vs. temperature max11044 toc09 temperature (c) shutdown current (a) 60 35 10 -15 1 2 3 4 5 0 -40 85 v avdd = 5.0v v dvdd = 3.3v i avdd i dvdd analog and digital shutdown current vs. supply voltage max11044 toc09a v avdd or v dvdd (v) shutdown current (a) 4.75 4.25 3.75 3.25 1 2 3 4 5 0 2.75 5.25 t a = +25c i avdd i dvdd internal reference voltage vs. temperature max1960 toc11 temperature (c) v refio (v) 60 35 -15 10 4.084 4.088 4.092 4.096 4.104 4.100 4.108 4.112 4.080 -40 85 upper typical limit v avdd = 5.0v lower typical limit offset error and offset error matching vs. temperature max11044 toc13 temperature (c) errors (%fs) 60 35 10 -15 -0.006 -0.002 0.002 0.006 0.010 -0.010 -40 85 f sample = 250ksps v avdd = 5.0v v refio = 4.096v offset error matching offset error internal reference voltages vs. supply voltage max1960 toc10 v avdd (v) v ref (v) 5.15 5.05 4.85 4.95 4.09595 4.09600 4.09605 4.09610 4.09620 4.09615 4.09625 4.09630 4.09590 4.75 5.25 v rdc t a = +25c v refio offset error and offset error matching vs. supply voltage max11044 toc12 v avdd (v) errors (%fs) 5.15 5.05 4.95 4.85 -0.006 -0.002 0.002 0.006 0.010 -0.010 4.75 5.25 f sample = 250ksps t a = +25c v rdc = 4.096v offset error matching offset error typical operating characteristics (continued) (v avdd = 5v, v dvdd = 3.3v, t a = +25c, f sample = 250ksps, internal reference, unless otherwise noted.)
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 8 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 gain error and gain error matching vs. supply voltage max11044 toc14 v avdd (v) errors (%fs) 5.15 5.05 4.95 4.85 -0.006 -0.002 0.002 0.006 0.010 -0.010 4.75 5.25 f sample = 250ksps t a = +25c v rdc = 4.096v gain error gain error matching gain error and gain error matching vs. temperature max11044 toc15 temperature (c) errors (%fs) 60 35 10 -15 -0.006 -0.002 0.002 0.006 0.010 -0.010 -40 85 f sample = 250ksps v avdd = 5.0v v refio = 4.096v gain error gain error matching fft plot (max1104_) max11044 toc16 frequency (khz) magnitude (db) 100 75 50 25 -120 -100 -80 -60 -40 -20 0 -140 0125 f in = 10khz f sample = 250ksps t a = +25c v avdd = 5.0v typical operating characteristics (continued) (v avdd = 5v, v dvdd = 3.3v, t a = +25c, f sample = 250ksps, internal reference, unless otherwise noted.) signal-to-noise ratio and signal-to-noise and distortion ratio vs. temperature (max1104_) max11044 toc18 temperature (c) snr and sinad (db) 60 35 10 -15 91 92 93 94 95 90 -40 85 f in = 10khz f sample = 250ksps t a = +25c v avdd = 5.0v v rdc = 4.096v v in = -0.025db from fs snr sinad snr and sinad vs. analog supply voltage (max1104_) max11044 toc20 v avdd (v) snr and sinad (db) 5.15 5.05 4.95 4.85 91.5 92.0 92.5 93.0 91.0 4.75 5.25 f in = 10khz f sample = 250ksps t a = +25c v rdc = 4.096v v in = -0.025db from fs snr sinad two-tone imd plot (max1104_) max11044 toc17 frequency (khz) magnitude (db) 12.0 11.2 10.4 9.6 8.8 8.0 7.2 12.8 f in1 = 9838hz f in2 = 10235hz f sample = 250ksps t a = +25c v avdd = 5.0v v rdc = 4.096v v in = -0.01dbfs -120 -100 -80 -60 -40 -20 0 -140 total harmonic distortion vs. temperature (max1104_) max11044 toc19 temperature (c) thd (db) 60 35 10 -15 -106.0 -105.5 -105.0 -104.5 -104.0 -103.5 -106.5 -40 85 f in = 10khz f sample = 250ksps t a = +25c v avdd = 5.0v v rdc = 4.096v v in = -0.025db from fs
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 9 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 thd vs. analog supply voltage (max1104_) max11044 toc21 v avdd (v) thd (db) 5.15 5.05 4.95 4.85 -106 -105 -104 -103 -102 -107 4.75 5.25 f in = 10khz f sample = 250ksps t a = +25c v rdc = 4.096v v in = -0.025db from fs signal-to-noise and distortion ratio vs. frequency (max1104_) max11044 toc22 frequency (khz) sinad (db) 10 1 84 86 88 90 92 94 82 0.1 100 f sample = 250ksps t a = +25c v avdd = 5.0v v rdc = 4.096v v in = -0.025db from fs thd vs . input frequency (max1104_) m ax11044 toc23 frequency (khz) thd (db) 10 1 -105 -100 -95 -90 -85 -110 0 . 1100 f sample = 250ksps t a = +25c v avdd = 5.0v v rdc = 4.096v v in = -0.025db from fs typical operating characteristics (continued) (v avdd = 5v, v dvdd = 3.3v, t a = +25c, f sample = 250ksps, internal reference, unless otherwise noted.) output noise histogram with input connected to agnds (max1104_) max11044 toc25 output code (decimal) number of occurances 50,000 100,000 150,000 200,000 0 32765 32766 32767 32768 32769 32770 32771 v ch_ = 0v v avdd = 5.0v v rdc = 4.096v f sample = 250ksps conversion time vs. temperature max11044 toc27 temperature (c) conversion time (s) 60 35 -15 10 2.93 2.94 2.95 2.96 2.98 2.97 2.99 3.00 2.92 -40 85 v avdd = 5.0v crosstalk vs . frequency m ax11044 toc24 frequency (khz) crosstalk (db) 10 1 -130 -120 -110 -100 -90 -140 0 . 1 100 f in = 60hz f sample = 250ksps t a = +25c v avdd = 5.0v v rdc = 4.096v v in = -0.025db from fs inactive channel at agnds conversion time vs. analog supply volatage max11044 toc26 v avdd (v) conversion time (s) 5.15 5.05 4.85 4.95 2.93 2.94 2.95 2.96 2.98 2.97 2.99 3.00 2.92 4.75 5.25 t a = +25c
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 10 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 pin description pin max11044 (tqfn-ep) MAX11045 (tqfn-ep) max11046 (tqfn-ep) name function 1 1 1 db13 16-bit parallel data bus digital output bit 13 2 2 2 db12 16-bit parallel data bus digital output bit 12 3 3 3 db11 16-bit parallel data bus digital output bit 11 4 4 4 db10 16-bit parallel data bus digital output bit 10 5 5 5 db9 16-bit parallel data bus digital output bit 9 6 6 6 db8 16-bit parallel data bus digital output bit 8 7, 21, 50 7, 21, 50 7, 21, 50 dgnd digital ground 8, 20, 51 8, 20, 51 8, 20, 51 dvdd digital supply. bypass to dgnd with a 0.1f capacitor at each dvdd input. 9 9 9 db7 16-bit parallel data bus digital output bit 7 10 10 10 db6 16-bit parallel data bus digital output bit 6 11 11 11 db5 16-bit parallel data bus digital output bit 5 12 12 12 db4 16-bit parallel data bus digital output bit 4 13 13 13 db3/cr3 16-bit parallel data bus digital output bit 3/ configuration register input bit 3 14 14 14 db2/cr2 16-bit parallel data bus digital output bit 2/ configuration register input bit 2 15 15 15 db1/cr1 16-bit parallel data bus digital output bit 1/ configuration register input bit 1 16 16 16 db0/cr0 16-bit parallel data bus digital output bit 0/ configuration register input bit 0 17 17 17 eoc active-low end-of-conversion output. eoc goes low when conversion is completed. eoc goes high when a conversion is initiated. 18 18 18 convst c onver t s tar t inp ut. ri si ng ed g e of c on v s t end s sam p l e and star ts a conver si on on the cap tur ed sam p l e. the ad c i s i n acq ui si ti on m od e w hen c on v s t i s l ow and c on v s t m od e = 0. 19 19 19 shdn shutdown input. if shdn is held high, the entire device will enter and stay in a low-current state. contents of the configuration register are not lost when in the shutdown mode. 22, 28, 35, 43, 49 22, 28, 35, 43, 49 22, 28, 35, 43, 49 rdc refer ence buffer d ecoup l i ng . c onnect al l rd c outp uts tog ether . byp ass to ag n d w i th at l east an 80f total cap aci tance. s ee the layout, gr ound i ng , and byp assi ng secti on. 23, 27, 33, 38, 44, 48 23, 27, 33, 38, 44, 48 23, 27, 33, 38, 44, 48 agnds signal ground. connect all agnd and agnds inputs together on pcb.
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 11 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 pin description (continued) pin max11044 (tqfn-ep) MAX11045 (tqfn-ep) max11046 (tqfn-ep) name function 24, 30, 41, 47 24, 30, 41, 47 24, 30, 41, 47 avdd analog supply input. bypass avdd to agnd with a 0.1f capacitor at each avdd input. 25, 31, 40, 46 25, 31, 40, 46 25, 31, 40, 46 agnd analog ground. connect all agnd inputs together. 32 29 26 ch0 channel 0 analog input 34 32 29 ch1 channel 1 analog input 37 34 32 ch2 channel 2 analog input 39 37 34 ch3 channel 3 analog input 36 36 36 refio external reference input/internal reference output. place a 0.1f capacitor from refio to agnd. 39 37 ch4 channel 4 analog input 42 39 ch5 channel 5 analog input 42 ch6 channel 6 analog input 45 ch7 channel 7 analog input 52 52 52 wr active-low write input. drive wr low to write to the adc. configuration registers are loaded on the rising edge of wr . 53 53 54 cs active-low chip-select input. drive cs low when reading from or writing to the adc. 54 54 54 rd active-low read input. drive rd low to read from the adc. each rising edge of rd advances the channel output on the data bus. 55 55 55 db15 16-bit parallel data bus digital output bit 15 56 56 56 db14 16-bit parallel data bus digital output bit 14 26, 29, 42, 45 26, 45 i.c. internally connected. connect to agnd. ep e xp osed p ad . inter nal l y connected to ag n d . c onnect to a l ar g e g r ound p l ane to m axi m i ze ther m al p er for m ance. n ot i ntend ed as an el ectr i cal connecti on p oi nt.
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 12 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 pin description (continued) pin max11044 (tqfp-ep) MAX11045 (tqfp-ep) max11046 (tqfp-ep) name function 1 1 1 db14 16-bit parallel data bus digital output bit 14 2 2 2 db13 16-bit parallel data bus digital output bit 13 3 3 3 db12 16-bit parallel data bus digital output bit 12 4 4 4 db11 16-bit parallel data bus digital output bit 11 5 5 5 db10 16-bit parallel data bus digital output bit 10 6 6 6 db9 16-bit parallel data bus digital output bit 9 7 7 7 db8 16-bit parallel data bus digital output bit 8 8, 22, 59 8, 22, 59 8, 22, 59 dgnd digital ground 9, 21, 60 9, 21, 60 9, 21, 60 dvdd digital supply. bypass to dgnd with a 0.1f capacitor at each dvdd input. 10 10 10 db7 16-bit parallel data bus digital output bit 7 11 11 11 db6 16-bit parallel data bus digital output bit 6 12 12 12 db5 16-bit parallel data bus digital output bit 5 13 13 13 db4 16-bit parallel data bus digital output bit 4 14 14 14 db3/cr3 16-bit parallel data bus digital output bit 3/ configuration register input bit 3 15 15 15 db2/cr2 16-bit parallel data bus digital output bit 2/ configuration register input bit 2 16 16 16 db1/cr1 16-bit parallel data bus digital output bit 1/ configuration register input bit 1 17 17 17 db0/cr0 16-bit parallel data bus digital output bit 0/ configuration register input bit 0 18 18 18 eoc active-low end-of-conversion output. eoc goes low when conversion is completed. eoc goes high when a conversion is initiated. 19 19 19 convst c onver t s tar t inp ut. ri si ng ed g e of c on v s t end s sam p l e and star ts a conver si on on the cap tur ed sam p l e. the ad c i s i n acq ui si ti on m od e w hen c on v s t i s l ow and c on v s t m od e = 0. 20 20 20 shdn shutdown input. if shdn is held high, the entire device will enter and stay in a low-current state. contents of the configuration register are not lost when in the shutdown mode. 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 agnds signal ground. connect all agnd and agnds inputs together on pcb. 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 avdd analog supply input. bypass avdd to agnd with a 0.1f capacitor at each avdd input. 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 agnd analog ground. connect all agnd inputs together.
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 13 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 pin description (continued) pin max11044 (tqfp-ep) MAX11045 (tqfp-ep) max11046 (tqfp-ep) name function 26, 55 26, 55 26, 55 rdc_sense reference buffer sense feedback. connect to rdc plane. 27, 33, 40, 48, 54 27, 33, 40, 48, 54 27, 33, 40, 48, 54 rdc refer ence buffer d ecoup l i ng . c onnect al l rd c outp uts tog ether . byp ass to ag n d w i th at l east an 80f total cap aci tance. s ee the layout, gr ound i ng , and byp assi ng secti on. 37 34 31 ch0 channel 0 analog input 39 37 34 ch1 channel 1 analog input 42 39 37 ch2 channel 2 analog input 44 42 39 ch3 channel 3 analog input 41 41 41 refio external reference input/internal reference output. place a 0.1f capacitor from refio to agnd. 44 42 ch4 channel 4 analog input 47 44 ch5 channel 5 analog input 47 ch6 channel 6 analog input 50 ch7 channel 7 analog input 61 61 61 wr active-low write input. drive wr low to write to the adc. configuration registers are loaded on the rising edge of wr . 62 62 62 cs active-low chip-select input. drive cs low when reading from or writing to the adc. 63 63 63 rd active-low read input. drive rd low to read from the adc. each rising edge of rd advances the channel output on the data bus. 64 64 64 db15 16-bit parallel data bus digital output bit 15 31, 34, 47, 50 31, 50 i.c. internally connected. connect to agnd. ep e xp osed p ad . inter nal l y connected to ag n d . c onnect to a l ar g e g r ound p l ane to m axi m i ze ther m al p er for m ance. n ot i ntend ed as an el ectr i cal connecti on p oi nt.
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 14 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 pin description (continued) pin max11054 (tqfp-ep) max11055 (tqfp-ep) max11056 (tqfp-ep) name function 1 1 1 db12 14-bit parallel data bus digital output bit 12 2 2 2 db11 14-bit parallel data bus digital output bit 11 3 3 3 db10 14-bit parallel data bus digital output bit 10 4 4 4 db9 14-bit parallel data bus digital output bit 9 5 5 5 db8 14-bit parallel data bus digital output bit 8 6 6 6 db7 14-bit parallel data bus digital output bit 7 7 7 7 db6 14-bit parallel data bus digital output bit 6 8, 22, 59 8, 22, 59 8, 22, 59 dgnd digital ground 9, 21, 60 9, 21, 60 9, 21, 60 dvdd digital supply. bypass to dgnd with a 0.1f capacitor at each dvdd input. 10 10 10 db5 14-bit parallel data bus digital output bit 5 11 11 11 db4 14-bit parallel data bus digital output bit 4 12 12 12 db3 14-bit parallel data bus digital output bit 3 13 13 13 db2 14-bit parallel data bus digital output bit 2 14 14 14 db1/cr3 14-bit parallel data bus digital output bit 1/ configuration register input bit 3 15 15 15 db0/cr2 14-bit parallel data bus digital output bit 0/ configuration register input bit 2 16 16 16 cr1 configuration register input bit 1 17 17 17 cr0 configuration register input bit 0 18 18 18 eoc active-low end-of-conversion output. eoc goes low when conversion is completed. eoc goes high when a conversion is initiated. 19 19 19 convst c onver t s tar t inp ut. ri si ng ed g e of c on v s t end s sam p l e and star ts a conver si on on the cap tur ed sam p l e. the ad c i s i n acq ui si ti on m od e w hen c on v s t i s l ow and c on v s t m od e = 0. 20 20 20 shdn shutdown input. if shdn is held high, the entire device will enter and stay in a low-current state. contents of the configuration register are not lost when in the shutdown mode. 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 agnds signal ground. connect all agnd and agnds inputs together on pcb. 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 avdd analog supply input. bypass avdd to agnd with a 0.1f capacitor at each avdd input. 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 agnd analog ground. connect all agnd inputs together. 26, 55 26, 55 26, 55 rdc_sense refer ence buffer s ense feed b ack. c onnect to rd c p l ane.
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 15 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 detailed description the max11044/MAX11045/max11046 and max11054/ max11055/max11056 are fast, low-power adcs that combine 4, 6, or 8 independent adc channels in a sin- gle ic. each channel includes simultaneously sampling independent t/h circuitry that preserves relative phase information between inputs making the max11044/ MAX11045/max11046 and max11054/max11055/ max11056 ideal for motor control and power monitor- ing. the max11044/MAX11045/max11046 and max11054/max11055/max11056 are available with 5v input ranges that feature 20ma overrange, fault- tolerant inputs. the max11044/MAX11045/max11046 and max11054/max11055/max11056 operate with a single 4.75v to 5.25v supply. a separate 2.7v to 5.25v supply for digital circuitry makes the devices compatible with low-voltage processors. the max11044/MAX11045/max11046 and max11054/ max11055/max11056 perform conversions for all chan- nels in parallel by activating independent adcs. results are available through a high-speed, 20mhz, parallel data bus after a conversion time of 3s following the end of a sample. the data bus is bidirectional and allows for easy programming of the configuration register. the max11044/MAX11045/max11046 and max11054/ max11055/max11056 feature a reference buffer, which pin description (continued) pin max11054 (tqfp-ep) max11055 (tqfp-ep) max11056 (tqfp-ep) name function 27, 33, 40, 48, 54 27, 33, 40, 48, 54 27, 33, 40, 48, 54 rdc refer ence buffer d ecoup l i ng . c onnect al l rd c outp uts tog ether . byp ass to ag n d w i th at l east an 80f total cap aci tance. s ee the layout, gr ound i ng , and byp assi ng secti on. 37 34 31 ch0 channel 0 analog input 39 37 34 ch1 channel 1 analog input 42 39 37 ch2 channel 2 analog input 44 42 39 ch3 channel 3 analog input 41 41 41 refio external reference input/internal reference output. place a 0.1f capacitor from refio to agnd. 44 42 ch4 channel 4 analog input 47 44 ch5 channel 5 analog input 47 ch6 channel 6 analog input 50 ch7 channel 7 analog input 61 61 61 wr active-low write input. drive wr low to write to the adc. configuration registers are loaded on the rising edge of wr . 62 62 62 cs active-low chip-select input. drive cs low when reading from or writing to the adc. 63 63 63 rd acti ve- low read inp ut. d r i ve rd l ow to r ead fr om the ad c . e ach r i si ng ed g e of rd ad vances the channel outp ut on the d ata b us. 64 64 64 db13 14-bit parallel data bus digital output bit 13 31, 34, 47, 50 31, 50 i.c. internally connected. connect to agnd. ep e xp osed p ad . inter nal l y connected to ag n d . c onnect to a l ar g e g r ound p l ane to m axi m i ze ther m al p er for m ance. n ot i ntend ed as an el ectr i cal connecti on p oi nt.
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 16 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 is driven by an internal bandgap reference circuit (v re- fio = 4.096v). drive refio with an external reference or bypass with 0.1f capacitor to ground when using the internal reference. analog inputs track and hold (t/h) to preserve phase information across all channels, each input includes a dedicated t/h circuitry. the input tracking circuitry provides a 4mhz small-signal band- width, enabling the device to digitize high-speed tran- sient events and measure periodic signals with bandwidths exceeding the adcs sampling rate by using undersampling techniques. use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. input range and protection the full-scale analog input voltage is a product of the ref- erence voltage. for the max11044/MAX11045/ max11046 and max11054/max11055/max11056, the full-scale input is bipolar in the range of: when in external reference mode, drive v refio with a 3.0v to 4.25v source, resulting in an input range of 3.662v to 5.188v, respectively. all analog inputs are fault-protected to up to 20ma. the max11044/MAX11045/max11046 and max11054/ max11055/max11056 include an input clamping circuit that activates when the input voltage at the analog input is above (v avdd + 300mv) or below C(v avdd + 300mv). the clamp circuit remains high impedance while the input signal is within the range of v avdd and draws lit- tle or almost no current. however, when the input signal exceeds v avdd , the clamps begin to turn on and shunt current to/from the avdd supply. consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed (v avdd + 0.3v). to make use of the input clamps (see figure 1), con- nect a resistor (r s ) between the analog input and the voltage source to limit the voltage at the analog input so that the fault current into the max11044/MAX11045/ max11046 and max11054/max11055/max11056 does not exceed 20ma. note that the voltage at the analog input pin limits to approximately 7v during a fault condi- tion so the following equation can be used to calculate the value of r s : ( . ) vx refio 5 4 096 max11044/MAX11045/max11046/ max11054/max11055/max11056 clamp s/h 16-/14-bit adc clamp s/h 16-/14-bit adc ref buf configuration registers interface and control bandgap reference 8 x 16-/1 4-bit registers bidirectional dr ivers ch0 source avdd agnds *connected internally on the tqfn parts to rdc **max11044/MAX11045/max11046 ? max11046/max11056 agnd ch7 ? db15** db0/cr0 db3/cr3 db4 eoc shdn convst cs rd wr dgnd dvdd rdc rdc_sense* refio int ref 10k ? ext ref r s input signal pin voltage figure 1. required setup for clamp circuit
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 17 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 where v fault_max is the maximum voltage that the source produces during a fault condition. figures 2 and 3 illustrate the clamp circuit voltage-cur- rent characteristics for a source impedance r s = 1280 ? . while the input voltage is within the (v avdd + 300mv) range, no current flows in the input clamps. once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. applications information digital interface the bidirectional, parallel, digital interface, cr0Ccr3, sets the 4-bit configuration register. this interface con- figures the following control signals: chip select ( cs ), read ( rd ), write ( wr ), end of conversion ( eoc ), and convert start (convst). figures 6 and 7 and the timing characteristics in the electrical characteristics table show the operation of the interface. db0Cdb15/db13 output the 16-/14-bit conversion result. all bits are high impedance when rd = 1 or cs = 1. cr3 (int/ext reference) cr3 selects the internal or external reference. the por default = 0. 0 = internal reference, refio internally driven through a 10k ? resistor, bypass with 0.1f capacitor to agnd. 1 = external reference, drive refio with a high-quality reference. cr2 (output data format) cr2 selects the output data format. the por default = 0. 0 = offset binary. 1 = twos complement. cr1 (reserved) cr1 must be set to 0. cr0 (convst mode) cr0 selects the acquisition mode. the por default = 0. 0 = convst controls the acquisition and conversion. drive convst low to start acquisition. the rising edge of convst begins the conversion. 1 = acquisition mode starts as soon as the previous conversion is complete. the rising edge of convst begins the conversion. programming the configuration register to program the configuration register, bring the cs and wr low and apply the required configuration data on cr3Ccr0 of the bus and then raise wr once to save changes. caution: when the configuration register is not being programmed, the host driving cr3?r0 must relinquish the bus when the conversion results of the adc are being read! r vv ma s fault max _ = -7 20 cr3 cr2 cr1 cr0 int/ext reference output data format must be set to 0 convst mode table 1. configuration register max11044 fig02 signal voltage at source and pin (v) i clamp (ma) -10 -30 30 10 30 -30 10 -10 -20 20 0 -50 50 r s = 1280 ? v avdd = 5v at ch_ input at source figure 2. input clamp characteristics max11044 fig03 signal voltage at source and pin (v) i clamp (ma) -4 -6 246 0 -2 30 -30 10 -10 -20 20 0 -8 8 r s = 1280 ? v avdd = 5v at ch_ input at source figure 3. input clamp characteristics (zoom in)
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 18 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 starting a conversion convst initiates conversions. the max11044/ MAX11045/max11046 and max11054/max11055/ max11056 provide two acquisition modes set through the configuration register. allow a quiet time (t q ) of 500ns prior to the start of conversion to avoid any noise interference during readout or write operations from corrupting a sample. in default mode (cr0 = 0), drive convst low to place the max11044/MAX11045/max11046 and max11054/ max11055/max11056 into acquisition mode. all the input switches are closed and the internal t/h circuits track the respective input voltage. keep the convst signal low for at least 1s (t acq ) to enable proper set- tling of the sampled voltages. on the rising edge of convst, the switches are opened and the max11044/MAX11045/max11046 and max11054/ max11055/max11056 begin the conversion on all the samples in parallel. eoc remains high until the conver- sion is completed. in the second mode (cr0 = 1), the max11044/ MAX11045/max11046 and max11054/max11055/ max11056 enter acquisition mode as soon as the previ- ous conversion is completed. convst rising edge initi- ates the next sample and conversion sequence. convst needs to be low for at least 20ns to be valid. provide adequate time for acquisition and the requisite quiet time in both modes to achieve accurate sampling and maximum performance of the max11044/ MAX11045/max11046 and max11054/max11055/ max11056. reading conversion results the cs and rd are active-low, digital inputs that con- trol the readout through the 16-/14-bit, parallel, 20mhz data bus (d0Cd15/d13). after eoc transitions low, read the conversion data by driving cs and rd low. each low period of rd presents the next channels result. when cs or rd are high, the data bus is high imped- ance. cs may be driven high between individual chan- nel readouts or left low during the entire 8-channel readout. reference internal reference the max11044/MAX11045/max11046 and max11054/ max11055/max11056 feature a precision, low-drift, internal bandgap reference. bypass refio with a 0.1f capacitor to agnd to reduce noise. the refio output voltage may be used as a reference for other circuits. the output impedance of refio is 10k ? . drive only high impedance circuits or buffer externally when using refio to drive external circuitry. external reference set the configuration register to disable the internal ref- erence and drive refio with a high-quality external ref- erence. to avoid signal degradation, ensure that the integrated reference noise applied to refio is less than 10v in the bandwidth of up to 50khz. s n s n + 1 t 8 t 12 t 13 t 9 t 10 t 11 rd (user supplied) cs (user supplied) db0?db15/db13 figure 5. readout timing requirements configuration register t 6 t 3 t 4 t 5 t 7 wr (user supplied) cs (user supplied) cr0?cr3 (user supplied) figure 4. programming configuration-register timing requirements
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 19 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 s 0 s 1 s 6 s 7 sample t q t acq t 2 t con t o convst eoc rd db0?db15/db13 cs figure 7. conversion timing diagram (cr0 = 1) s 0 s 1 s 6 s 7 sample t q t acq t con t o t 1 convst eoc rd db0?db15/db13 cs figure 6. conversion timing diagram (cr0 = 0)
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 20 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 reference buffer the max11044/MAX11045/max11046 and max11054/ max11055/max11056 have a built-in reference buffer to provide a low-impedance reference source to the sar converters. this buffer is used in both internal and external reference mode. the reference buffer output feeds five rdc pins. the rdc pins should be all con- nected together on the pcb. the reference buffer is externally compensated and requires at least 10f on the rdc node. for best performance, provide a total of at least 80f on the rdc outputs. transfer functions figures 8 and 9 show the transfer functions for all the formats and devices. code transitions occur halfway between successive-integer lsb values. -fs 7fff 0001 0000 8000 8001 fffe input voltage (lsb) output code (hex) ffff 0 full-scale transition +fs +32,766.5 x v lsb -32,767.5 x v lsb -fs = -32,768 x v lsb 7ffe +fs = 32,767 x v lsb v lsb = (10/4.096) x (v ref /65,536) + 32,768 output code = v lsb v in figure 8. twos complement transfer function for 16-bit devices -fs 1fff 0001 0000 2000 2001 3ffe input voltage (lsb) output code (hex) 3fff 0 full-scale transition +fs +8190.5 x v lsb -8191.5 x v lsb -fs = -8192 x v lsb 1ffe +fs = 8191 x v lsb v lsb = (10/4.096) x (v ref /16,384) output code = v lsb v in + 8192 figure 9. offset-binary transfer function for 16-bit devices output code (hex) full-scale transition -fs ffff 8001 8000 0000 0001 7ffe input voltage (lsb) 7fff 0 +fs fffe output code = v lsb = (10/4.096) x (v ref /65,536) -fs = -32,768 x v lsb +fs = 32,767 x v lsb +32,766.5 x v lsb -32,767.5 x v lsb v lsb v in figure 8b. twos complement transfer function for 14-bit devices output code (hex) full-scale transition -fs 3fff 2001 2000 0000 0001 1ffe input voltage (lsb) 1fff 0 +fs +8190.5 x v lsb -8191.5 x v lsb 3ffe v lsb = (10/4.096) x (v ref /16,384) output code = v lsb v in -fs = -8192 x v lsb +fs = 8191 x v lsb figure 9b. offset-binary transfer function for 14-bit devices
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 21 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 max11046/ max11056 adc adc adc adc adc adc adc adc i3 v3 i2 v2 phase 2 phase 1 phase 3 load 2 load 1 vn in neutral load 3 opt opt current transformer voltage transformer figure 10. power-grid protection
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 22 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 16-/14-bit adc max11044/ MAX11045/ max11046/ max11054/ max11055/ max11056 16-/14-bit adc 16-/14-bit adc 16-/14-bit adc 16-/14-bit adc position encoder dsp-based digital processing engine igbt current drivers i phase1 3-phase electric motor i phase3 i phase2 figure 11. dsp motor control
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 23 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 layout, grounding, and bypassing for best performance use pcbs with ground planes. ensure that digital and analog signal lines are separated from each other. do not run analog and digital lines paral- lel to one another (especially clock lines), and avoid run- ning digital lines underneath the adc package. a single solid gnd plane configuration with digital signals routed from one direction and analog signals from the other pro- vides the best performance. connect dgnd, agnd, and agnds pins on the max11044/MAX11045/max11046 and max11054/max11055/max11056 to this ground plane. keep the ground return to the power supply for this ground low impedance and as short as possible for noise- free operation. to achieve the highest performance, connect all the rdc pins (22, 28, 35, 43, 49 for the tqfn package, or pins 27, 33, 40, 48, 54 for the tqfp package) to a local rdc plane on the pcb. in addition, on the tqfp pack- age, the rdc_sense pins 26 and 55 should be directly connected to this rdc plane as well. bypass the rdc outputs with a total of at least 80f of capacitance. if two capacitors are used, place each as close as possi- ble to pins 22 and 49 (tqfn) or pins 27 and 54 (tqfp). if four capacitors are used, place each as close as pos- sible to pins 22, 28, 43, and 49 (tqfn) or pins 27, 33, 48, and 54 (tqfp). for example, two 47f, 10v x5r capacitors in 1210 case size can be placed as close as possible to pins 22 and 49 (tqfn package) will provide excellent performance. alternatively, four 22f, 10v x5r capacitors in 1210 case size placed as close as possible to pins 22, 28, 43, and 49 (tqfn package) will also provide good performance. ensure that each capacitor is connected directly into the agnd plane with an independent via. if y5u or z5u ceramics are used, be aware of the high- voltage coefficient these capacitors exhibit and select higher voltage rating capacitors to ensure that at least 80f of capacitance is on the rdc plane when the plane is driven to 4.096v by the built-in reference buffer. for example, a 22f x5r with a 10v rating is approximately 20f at 4.096v, whereas, the same capacitor in y5u ceramic is just 13f. however, a y5u 22f capacitor with a 25v rating cap is approximately 20f at 4.096v. bypass avdd and dvdd to the ground plane with 0.1f ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. add at least one bulk 10f decoupling capacitor to avdd and dvdd per pcb. interconnect all of the avdd inputs and dvdd inputs using two solid power planes. for best performance, bring the avdd power plane in on the analog interface side of the max11044/ MAX11045/max11046 and max11054/max11055/ max11056 and the dvdd power plane from the digital interface side of the device. for acquisition periods near minimum (1s) use a 1nf c0g ceramic chip capacitor between each of the chan- nel inputs to the ground plane as close as possible to the max11044/MAX11045/max11046 and max11054/ max11055/max11056. this capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. typical application circuits power-grid protection figure 10 shows a typical power-grid protection application. dsp motor control figure 11 shows a typical dsp motor control application. definitions integral nonlinearity (inl) inl is the deviation of the values on an actual transfer function from a straight line. for these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step width and the ideal value of 1 lsb. for these devices, the dnl of each digital output code is measured and the worst-case value is reported in the electrical characteristics table. a dnl error specification of greater than -1 lsb guaran- tees no missing codes and a monotonic transfer func- tion. for example, -0.9 lsb guarantees no missing code while -1.1 lsb results in missing code. offset error the offset error is defined as the input voltage required to cause the max11044/MAX11045/max11046 digital output to be centered on code 0x8000 (offset binary) or 0x0000 (twos complement) and the max11054/ max11055/max11056 digital output to be centered on code 0x0000 (offset binary) or 0x0000 (twos comple- ment). ideally, this input voltage should be 0v with respect to agnds. gain error gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtract- ed from the ideal change in analog input voltage on (10/4.096) x v ref x (65,534/65,536) for 16-bit, or (10/4.096) x v ref x (16,382/16,384) for 14-bit devices. for the max11044/MAX11045/max11046, top code tran-
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 24 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 sition is 0x7ffe to 0x7fff in twos complement mode and 0xfffe to 0xffff in offset binary mode. the bottom code transition is 0x8000 and 0x8001 in twos comple- ment mode and 0x0000 and 0x0001 in offset binary mode. for the max11054/max11055/max11056, top code transition is 0x1ffe to 0x1fff in twos complement mode and 0x3ffe to 0x3fff in offset binary mode. the bottom code transition is 0x2000 and 0x2001 in twos complement mode and 0x0000 and 0x0001 in offset bina- ry mode. for the max11044/MAX11045/max11046 and max11054/max11055/max11056, the analog input volt- age to produce these code transitions is measured and the gain error is computed by subtracting (10/4.096) x v ref x (65,534/65,536) or (10/4.096) x v ref x (16,382/16,384), respectively from this measurement. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76)db where n = 16/14 bits. in reality, there are other noise sources besides quantization noise: thermal noise, ref- erence noise, clock jitter, etc. snr is computed by tak- ing the ratio of the rms signal to the rms noise, which includes all spectral components not including the fun- damental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is the ratio of the fundamental input frequencys rms amplitude to the rms equivalent of all the other adc output signals: effective number of bits (enob) the enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantization noise only. with an input range equal to the full-scale range of the adc, calculate the enob as follows: total harmonic distortion (thd) thd is the ratio of the rms of the first five harmonics of the input signal to the fundamental itself. this is: expressed as: where v 1 is the fundamental amplitude and v 2 through v 5 are the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the funda- mental (maximum signal component) to the rms value of the next-largest frequency component. aperture delay aperture delay (t ad ) is the time delay from the sampling clock edge to the instant when an actual sample is taken. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in aperture delay. channel-to-channel isolation channel-to-channel isolation indicates how well each analog input is isolated from the other channels. channel-to-channel isolation is measured by applying dc to channels 1 to 7, while a -0.4dbfs sine wave at 60hz is applied to channel 0. a 10ksps fft is taken for channel 0 and channel 1. channel-to-channel isolation is expressed in db as the power ratio of the two 60hz magnitudes. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in a manner that ensures that the signals slew rate does not limit the adcs performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3db. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as full- power input bandwidth frequency. thd vvvv v = +++ ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log enob sinad = ? 176 602 . . sinad db signal noise distortion rms rms ( ) log () = + ? ? ? ? ? ? 10
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 25 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 top view max11044 MAX11045 max11046 tqfn 8mm x 8mm + 15 17 16 18 19 20 21 22 23 24 25 26 27 28 db1/cr1 *ep db0/cr0 eoc convst shdn dvdd dgnd rdc agnds avdd agnd ch0*/i.c. ?? agnds rdc db14 db15 rd cs wr dvdd dgnd rdc agnds avdd agnd i.c. ?? /ch7* ? max11044 ? MAX11045 *max11046 agnds rdc 48 47 46 45 44 43 54 53 56 55 52 51 50 49 1 2 3 4 5 6 7 8 9 1011121314 42 41 40 39 38 37 36 35 34 33 32 31 30 29 db4 cr3/db3 cr2/db2 db5 db6 db7 dvdd dgnd db8 db9 db10 db11 db12 db13 agnd avdd ch1*/ch0 ? /i.c. ? ch2*/ch1 ? /ch0 ? agnds ch3*/ch2 ? /ch1 ? rdc refio ch4*/ch3 ? /ch2 ? agnds ch5*/ch4 ? /ch3 ? agnd avdd ch6*/ch5 ? /i.c. ? max11044 MAX11045 max11046 tqfp 10mm x 10mm + 19 21 20 22 23 24 25 26 27 28 29 30 31 32 *ep eoc convst shdn dvdd dgnd agnds avdd agnd rdc_sense rdc agnds avdd agnd ch0*/i.c. ?? agnds dgnd agnds rd cs wr avdd agnd rdc_sense rdc agnds avdd agnd i.c. ?? /ch7* agnds 54 53 52 51 50 49 60 59 62 61 58 57 56 55 1 2 3 4 5 6 7 8 9 1011121314 48 47 46 45 44 43 42 41 40 39 38 37 36 35 db5 db4 cr3/db3 db6 db7 dvdd dgnd db8 db9 db10 db11 db12 db13 db14 ch2*/ch1 ? /ch0 ? agnd avdd agnds ch3*/ch2 ? /ch1 ? rdc refio ch4*/ch3 ? /ch2 ? agnds ch5*/ch4 ? /ch3 ? agnd avdd ch6*/ch5 ? /i.c. ? rdc 15 16 cr2/db2 cr1/db1 34 33 ch1*/ch0 ? /i.c. ? rdc 17 18 db0/cr0 db15 dvdd 64 63 pin configurations positive full-scale error the error in the input voltage that causes the last code transition of fffe to ffff (hex) for 16-bit or 3ffe to 3fff (hex) for 14-bit devices (in default offset binary mode) or 7ffe to 7fff (hex) for 16-bit or 1ffe to 1fff (hex) for 14- bit devices (in twos complement mode) from the ideal input voltage of 32,766.5 x (10/4.096) x (v ref /65,536) for 16-bit or 8190.5 x (10/4.096) x (v ref /16,384) for 14-bit devices after correction for offset error. negative full-scale error the error in the input voltage that causes the first code transition of 0000 to 0001 (hex) (in default offset binary mode) or 8000 to 8001 (hex) for 16-bit or 2000 to 2001 (hex) for 14-bit devices (in twos complement mode) from the ideal input voltage of -32,767.5 x (10/4.096) x (v ref /65,536) for 16-bit or -8191.5 x (10/4.096) x (v ref /16,384) for 14-bit devices after correction for offset error. chip information process: bicmos
4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs 26 maxim integrated max11044/MAX11045/max11046/ max11054/max11055/max11056 max11054 max11055 max11056 + 19 21 20 22 23 24 25 26 27 28 29 30 31 32 *ep eoc convst shdn dvdd dgnd agnds avdd agnd rdc_sense rdc agnds avdd agnd ch0*/i.c. ?? agnds dgnd agnds rd cs wr avdd agnd rdc_sense rdc agnds avdd agnd i.c. ?? /ch7* agnds 54 53 52 51 50 49 60 59 62 61 58 57 56 55 1 2 3 4 5 6 7 8 9 1011121314 48 47 46 45 44 43 42 41 40 39 38 37 36 35 ch2*/ch1 ? /ch0 ? agnd avdd agnds ch3*/ch2 ? /ch1 ? rdc refio ch4*/ch3 ? /ch2 ? agnds ch5*/ch4 ? /ch3 ? agnd avdd ch6*/ch5 ? /i.c. ? rdc 15 16 34 33 ch1*/ch0 ? /i.c. ? rdc 17 18 cr0 db13 dvdd 64 63 ? max11054 ? max11055 *max11056 tqfp 10mm x 10mm db3 db2 cr3/db1 db4 db5 dvdd dgnd db6 db7 db8 db9 db10 db11 db12 cr2/db0 cr1 pin configurations (continued) package type package code outline no. land pattern no. 56 tqfn-ep t5688+3 21-0135 90-0047 64 tqfp-ep c64e+6 21-0084 90-0328 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per tains to the package regardless of rohs status.
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integr ated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time . the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ________________________________ 27 ? 2011 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products , inc. 4-/6-/8-channel, 16-/14-bit, simultaneous-sampling adcs max11044/MAX11045/max11046/ max11054/max11055/max11056 revision history revision number revision date description pages changed 0 10/09 initial release 1 3/10 added tqfp package to data sheet 1, 2, 8, 9, 19 2 5/10 added 14-bit max11054/max11055/max11056 1C4, 7, 9C26 3 9/10 style edits, specified part numbers in typical operating characteristics , corrected pin names, clarified layout 1, 3C8, 13C18, 22 4 10/10 released the tqfp versions of max11044, MAX11045, and max11046. revised the electrical characteristics , typical operating characteristics , and the input range and protection section. 1C8, 15 5 1/11 released max11054, max11055, max11056. revised the electrical characteristics and figures 8b and 9b. 1, 2, 4, 20

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